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ISD4004 series publication release date: oct 31, 2008 - 1 - revision 1.31 ISD4004 series single-chip, multiple-messages voice record/playback devices 8-, 10-, 12-, and 16-minute duration www.datasheet.co.kr datasheet pdf - http://www..net/
ISD4004 series publication release date: oct 31, 2008 - 2 - revision 1.31 1. general description ............................................................................................................... 3 2. features .............................................................................................................................. ......... 4 3. block diagram ............................................................................................................................ 5 4. pin configuration ..................................................................................................................... 6 5. pin description .......................................................................................................................... 7 6. functional description ....................................................................................................... 12 6.1. detailed description ................................................................................................................ 12 6.2. serial peripheral interface (spi) description .......................................................................... 13 6.2.1 opcodes ....................................................................................................................... 14 6.2.2 spi diagrams ................................................................................................................... 15 6.2.3 spi control and output registers ................................................................................... 16 7. timing diagrams ....................................................................................................................... 18 8. absolute maximum ratings ................................................................................................. 20 8.1. operating conditions .............................................................................................................. 21 9. electrical characteristics ............................................................................................... 22 9.1. parameters for packaged parts ............................................................................................ 22 9.2. parameters for die ................................................................................................................. 25 9.3. spi ac parameters ................................................................................................................. 26 10. typical application circuit ................................................................................................ 27 11. packaging and die information ......................................................................................... 30 11.1. 28-lead 300-mil plastic small outline ic (soic) ............................................................... 30 11.2. 28-lead 600-mil plastic dual inline package (pdip) .......................................................... 31 11.3. 28-lead 8x13.4mm plastic thin small outline package (tsop) type 1 - iqc ................. 32 11.4. 28-lead 8x13.4mm plastic thin small outline package (tsop) type 1 ........................... 33 11.5. die information .................................................................................................................... 34 12. ordering information .......................................................................................................... 36 13. version history ....................................................................................................................... 37 www.datasheet.co.kr datasheet pdf - http://www..net/
ISD4004 series publication release date: oct 31, 2008 - 3 - revision 1.31 1. general description the ISD4004 chipcorder ? series provides high-quality, 3-volt, single-chip record/playback solutions for 8- to 16-minute messaging applications ideally for cellular phones and other portable products. the cmos-based devices include an on-chip oscillator, anti-aliasing filter, smoothing filter, automute ? feature, audio amplifier, and high density multileve l flash memory array. the ISD4004 series is designed to be used in a microprocessor- or micr ocontroller-based system. address and control are accomplished through a serial peripheral interface (spi) or microwire serial interface to minimize pin count. recordings are stored into the on-chip flash me mory cells, providing zero-power message storage. this unique single-chip solution utilizes nuvot on?s patented multilevel storage technology. voice and audio signals are directly stored onto memory array in their natural form, providing high-quality voice reproduction. www.datasheet.co.kr datasheet pdf - http://www..net/
ISD4004 series publication release date: oct 31, 2008 - 4 - revision 1.31 2. features ? single-chip voice record/playback solution ? single 3 volt supply ? low-power consumption ? operating current: - i cc_play = 15 ma (typical) - i cc_rec = 25 ma (typical) ? standby current: - i cc_standby = 1 a (typical) ? duration: 8, 10, 12, and 16 minutes ? high-quality, natural voice/audio reproduction ? automute feature provides background noise attenuation ? no algorithm development required ? microcontroller spi or microwire? serial interface ? fully addressable to handle multiple messages ? non-volatile message storage ? 100k record cycles (typical) ? 100-year message retention (typical) ? on-chip oscillator ? power-down feature to reduce power consumption ? available in die, pdip, soic, and tsop ? packaged type: lead-free ? temperature: - commercial (die): 0c to +50c - commercial (packaged units): 0c to +70c - industrial (packaged units): -40c to +85c www.datasheet.co.kr datasheet pdf - http://www..net/
ISD4004 series publication release date: oct 31, 2008 - 5 - revision 1.31 3. block diagram internal clock timing sampling clock 3,840k cell nonvolatile multilevel storage array analog transceivers decoders power conditioning 5-pole active antialiasing filter 5-pole active smoothing filter amp audout xclk v cca v ssa v ssa v ssa amp ana in- ana in+ automute tm feature device control v ssd v ccd sclk ss mosi miso int rac am cap www.datasheet.co.kr datasheet pdf - http://www..net/
ISD4004 series publication release date: oct 31, 2008 - 6 - revision 1.31 n+ n- 4. pin configuration soic / pdip ss mosi miso v ssd nc nc nc nc nc nc v ssa v ssa aud out am cap v ccd xclk int rac v ssa nc nc nc nc v cca ana i ana i nc sclk ISD4004 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ISD4004 nc nc v cca ana in+ ana in- nc am cap nc aud out v ssa v ssa nc nc nc nc v ssa rac nc nc int xclk v ccd sclk ss mosi miso v ssd nc tsop 1 2 3 4 5 6 7 8 9 10 11 12 13 28 27 26 25 24 23 22 21 20 19 18 17 16 14 15 www.datasheet.co.kr datasheet pdf - http://www..net/
ISD4004 series publication release date: oct 31, 2008 - 7 - revision 1.31 5. pin description pin name pin no. function soic / pdip tsop ss 1 9 slave select : this input, when low, will select the ISD4004 device. mosi 2 10 master out slave in : this is the serial input to the ISD4004 device when it is confi gured as slave. the master microcontroller places data on the mosi line one half-cycle before the rising edge of sclk fo r clocking into the device. miso 3 11 master in slave out : this is the serial output of the ISD4004 device. this output goes into a high-impedance state if the device is not selected. v ssa / v ssd 11, 12, 23 / 4 1, 17, 18 / 12 ground : the ISD4004 series utilizes separate analog and digital ground busses. the analog ground (v ssa ) pins should be tied together as close as possible and connected through a low-impedance path to power supply ground. the digital ground (v ssd ) pin should be connected through a separate low-impedance path to power supply ground. these ground paths should be large enough to ensure that the impedance between the v ssa pins and the v ssd pin is less than 3 ? . the backside of the die is connected to v ss through the substrate. for chip-on-board design, the die attach area must be connected to v ss or left floating. nc 5-10, 15, 19-22 3, 4, 13- 16, 19, 21, 23, 27, 28 not connected aud out [ 1 ] 13 20 audio output : this pin provides an audio output of the stored data and is recommended be ac coupled. it is capable of driving a 5 k ? impedance r ext . [1] the aud out pin is always at 1.2 volts when the dev ice is powered up. when in playback, the output buffer connected to this pin can dr ive a load as small as 5 k ? . when in record, a built-in resistor connects aud out to the internal 1.2-volt anal og ground supply. this resist or is approximately 850 k ? , but will vary somewhat according to the sample rate of the device. this rela tively high impedance allows this pin to be connected to an audio bus without loading it down. www.datasheet.co.kr datasheet pdf - http://www..net/
ISD4004 series publication release date: oct 31, 2008 - 8 - revision 1.31 pin name pin no. function soic / pdip tsop am cap 14 22 automute? feature : the automute feature only applies for playback operation and helps to minimize noise (with 6 db of attenuation) when there is no signal (i.e. during periods of silence). a 1 f capacitor to ground is recommended to connect to the am cap pin. this capacitor becomes a part of an internal peak detector which senses the signal amplitude. this peak level is compared to an internally set threshold to determine the automute trip point. for large signals, the automute attenuation is set to 0 db automatically but 6 db of attenuation occurs for silence. the 1 f capacitor also affects the rate at which the automute feature changes with the signal amplitude (or the attack time). the automute feature can be disabled by connecting the am cap pin directly to v cca .. ana in- 16 24 inverting analog input : this pin transfers the signal into the device during recording via differential-input mode. in this differential-input mode, a 16 mvp-p maximum input signal should be capacitively coupled to ana in- for optimal signal quality, as shown in figure 1: ana in modes. this capacitor value should be equal to that used on ana in+ pin. the input impedance at ana in- is normally 56 k ?. in the single-ended mode, ana in- should be capacitively coupled to v ssa through a capacitor equal to that used on the ana in+ pin. ana in+ 17 25 non-inverting analog input : this pin is the non-inverting analog input that transfers t he signal to the device for recording. the analog input amplifier can be driven single ended or differentially. in the single-ended input mode, a 32 mvp-p (peak-to-peak) maximum signal should be capacitively connected to this pin for optimal signal quality. the external capacitor associated with ana in+ together with the 3 k ? input impedance are selected to give cutoff at the low frequency end of the voice passband. in the differential-input mode, the maximum input signal at ana in+ should be 16 mvp-p capacitively coupled for optimal signal quality. the circuit connections for the two modes are shown in figure 1. www.datasheet.co.kr datasheet pdf - http://www..net/
ISD4004 series publication release date: oct 31, 2008 - 9 - revision 1.31 pin name pin no. function soic / tsop pdip v cca / v ccd 18 / 27 26 / 7 supply voltage : to minimize noises, the analog and digital circuits in the ISD4004 dev ices use separate power busses. these +3v busses are brought out to separate pins and should be tied together as close to the supply as possible. in addition, these supplies should be decoupled as close to the package as possible. rac 24 2 row address clock : this is an open drain output that provides the signal of a row with a 200 ms period for 8 khz sampling frequency. (this represents a single row of memory.) this signal stay s high for 175 ms and stays low for 25 ms when it reaches the end of a row. the rac pin stays high fo r 109.37 sec and stays low for 15.63 sec in message cueing mode (see message cueing section for detailed description). refer to the ac parameters table for rac timing information at other sample rates. when a record command is first initiated, the rac pin remains high for an extra t racl period. this is due to the need of loading the internal sample and hold circuits in the device. this pin can be used for message management techniques. a pull-up resistor is required to connect this pin to other device. int 25 5 interrupt : this is an open drain output pin. this pin goes low and stays low when an overflow (ovf) or end of message (eom) marker is detected. each operation that ends with an eom or ovf will generate an interrupt. the interrupt will be cleared the next time an spi cycle is initiated. the interrupt status can also be read by an r int instruction. a pull-up resistor is required to connect this pin to other device. overflow flag (ovf) ? the overflow flag indicates that the end of memory has been reached during a record or playback operation. end of message (eom) ? the end of message flag is set only during playback operation when an eom is found. there are eight eom flag position options per row. www.datasheet.co.kr datasheet pdf - http://www..net/
ISD4004 series publication release date: oct 31, 2008 - 10 - revision 1.31 pin name pin no. function soic / pdip tsop xclk 26 6 external clock input : the ISD4004 series is configured at the factory with an internal sampling clock frequency centered to 1 percent of specification. the frequency is then maintained to a variation of 2.25 percent over the entire commercial temperature and operating voltage ranges. the internal clock has a ?6/+4 percent tolerance over the industrial temperature and voltage ranges. a regulated power supply is recommended for industrial temperature range parts. if great er precision is required, the device can be clocked through the xclk pin as follows: part number sample rate required clock ISD4004-08m 8.0 khz 1024 khz ISD4004-10m 6.4 khz 819.2 khz ISD4004-12m 5.3 khz 682.7 khz ISD4004-16m 4.0 khz 512 khz these recommended clock rates should not be varied because the anti-aliasing and smoothing filters are fixed. otherwise, aliasing problems can occur if the sample rate differs from the one recommended. the duty cycle on the input clock is not critical, as the clock is immediately divided by two. if the xclk is not used, this input must be connected to ground. sclk 28 8 serial clock : this is the input clock to the ISD4004 device. it is generated by the master device (typically microcontoller) and is used to synchronize the data transfer in and out of the device through the mosi and miso lines, respectively. data is latched into the ISD4004 on the rising edge of sclk and shifted out of the device on the falling edge of sclk. www.datasheet.co.kr datasheet pdf - http://www..net/
ISD4004 series publication release date: oct 31, 2008 - 11 - revision 1.31 32m vp-p signal 0.1 f 0.1 f ana in+ ana in- 3k 3k 53k 53k 1.2v to filter internal to the device - + single-ended input mode 16m vp-p input signal 0.1 f 0.1 f ana in+ ana in- 3k 3k 53k 53k 1.2v to filter internal to the device - + differential input mode 16m vp-p 180 input signal figure 1: ISD4004 series ana in modes rac t rac (200 ms) 25 ms t racl figure 2: rac timing waveform during normal operation (example of 8khz sampling rate) www.datasheet.co.kr datasheet pdf - http://www..net/
ISD4004 series publication release date: oct 31, 2008 - 12 - revision 1.31 6. functional description 6.1. d etailed d escription audio quality the nuvoton?s ISD4004 chipcorder ? series is offered at 8.0, 6.4, 5.3 and 4.0 khz sampling frequencies, allowing the user a choice of speec h quality options. increasing the sampling frequency will produce better sound quality, but affects duration. please refer to table 1: product summary for details. analog speech samples are stored directly into on-ch ip non-volatile memory without the digitization and compression associated with other solutions. direct analog storage provides higher quality reproduction of voice, music, tones, and sound effects than other solid-state solutions. duration the ISD4004 series is a single-chip soluti on with 8-, 10-, 12-, and 16-minute duration. table 1: product summary of ISD4004 series part number duration (minutes) sample rate (khz) typical filter pass band (khz) * ISD4004-08m 8 8.0 3.4 ISD4004-10m 10 6.4 2.7 ISD4004-12m 12 5.3 2.3 ISD4004-16m 16 4.0 1.7 * this is the ?3db point. this parameter is not che cked during production testing and may vary due to process variations and other factors. theref ore, the customer should not rely upon this value for testing purposes. flash storage the ISD4004 series utilizes on-chip flash memo ry, providing zero-power message storage. the message is retained for up to 100 years typically without power. in addition, the device can be re- recorded typically over 100,000 times. memory architecture the ISD4004 series contains a total of 3,840k flas h memory cells, which is organized as 2,400 rows of 1,600 cells each. the address bits (a0-a15) are used to access various rows for multiple messages of different durations. www.datasheet.co.kr datasheet pdf - http://www..net/
ISD4004 series publication release date: oct 31, 2008 - 13 - revision 1.31 microcontroller interface a four-wire (sclk, mosi, miso & ss ) spi interface is provided for controlling and addressing functions. the ISD4004 is configured to operate as a peripheral slave device, with a microcontroller- based spi bus interface. read and write operations are controlled through this spi interface. an interrupt signal ( int ) and internal read only status regist er are provided for handshake purposes. programming the ISD4004 series is also ideal for playback-only applications, where single- or multiple-messages playback is controlled through the spi port. once the desired message configuration is created, duplicates can easily be generated via a programmer. 6.2. s erial p eripheral i nterface (spi) d escription the ISD4004 series operates via spi serial interface with the following protocol. first, the data transfer protocol assumes that the microcontroller?s spi shift registers are clocked on the falling edge of the sclk. however, for t he ISD4004, the protocols are as follows: 1. all serial data transfers begin with the falling edge of ss pin. 2. ss is held low during all serial communications and held high between instructions. 3. data is clocked in on the rising edge of t he sclk signal and clocked out on the falling edge of the sclk signal, with lsb first. 4. playback and record operations are initiat ed when the device is enabled by asserting the ss pin low, shifting in an opcode and an address data to the ISD4004 device (refer to the opcode summary in the following page). 5. the opcodes contain <16 address bits> and <8 control bits>. 6. each operation that ends with an eom or over flow will generate an interrupt. the interrupt will be cleared the next time a spi cycle is initiated. 7. as interrupt data is shifted out of t he miso pin, while address and control data are simultaneously shifted into the mosi pin. care s hould be taken such that the data shifted in is compatible with current system operation. bec ause it is possible to read an interrupt data and start a new operation within the same spi cycle. 8. an operation begins with the run bit set and ends with the run bit reset. 9. all operations begin after the rising edge of ss . www.datasheet.co.kr datasheet pdf - http://www..net/
ISD4004 series publication release date: oct 31, 2008 - 14 - revision 1.31 6.2.1 opcodes the available opcodes are summarized as follows: table 2: opcode summary instructions opcodes descriptions address (16 bits) control bits (8 bits) xxx c0 c1 c2 c3 c4 powerup xxx 0 0 1 0 0 power-up: device will be ready for an operation after t pud . setplay xxx 0 0 1 1 1 initiates playback from address . play xxx 0 1 1 1 1 playba ck from the current address (until eom or ovf). setrec xxx 0 0 1 0 1 initia tes a record operation from address . rec xxx 0 1 1 0 1 records from current address until ovf is reached or stop command is sent. setmc xxx 1 0 1 1 1 initiates message cueing (mc) from address . mc [ 1 ] xxx 1 1 1 1 1 performs a message cueing from current location. proceeds to the end of message (eom) or enters ovf condition if no more messages are present. stop xxx 0 1 1 x 0 stops the current operation. stoppwrdn xxx x 1 0 x 0 stops the current operation and enters into standby (power-down) mode. rint [ 2 ] xxx 0 1 1 x 0 read in terrupt status bits: overflow and eom. notes: c0 = message cueing c1 = ignore address bit c2 = master power control c3 = record or playback operation c4 = enable or disable an operation [1] message cueing can be selected only at the beginning of a playback operation. [2] as the interrupt data is shifted out of the ISD4004, control and address dat a are being shifted in. care should be taken such that the data shifted in is compatible with current system oper ation. it is possible to read interrupt data and start a new operation at the same time. see figures 5 - 8 for references. www.datasheet.co.kr datasheet pdf - http://www..net/
ISD4004 series publication release date: oct 31, 2008 - 15 - revision 1.31 6.2.2 spi diagrams output shift register miso mosi row counter a0-a15 p0-p15 (loaded to row counter only if iab = 0) ovf eom lsb p0 ... p15 input shift register select logic x x x lsb a0 a15 c 0 c 4 figure 3: spi interface simplified block diagram the following diagram describes the spi port and the control bits associated with it. miso ovf eom p0 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 0 0 0 0 0 0 lsb msb mosi a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 lsb msb c0 c1 c2 c3 c4 x x x message cueing (mc) ignore address bit (iab) power up (pu) play/record (p/r) run notes: 1. for mosi, lsb is the 1 st bit shifted into the ISD4004. 2. for miso, lsb is the 1 st bit shifted out from the ISD4004. figure 4: spi port www.datasheet.co.kr datasheet pdf - http://www..net/
ISD4004 series publication release date: oct 31, 2008 - 16 - revision 1.31 6.2.3 spi control and output registers the spi control register provides control of individual function such as play, record, message cueing, power-up, power-down, start, stop and ignore address pointer operations. table 3: spi control registers control bit control register bit device function c0 mc = = 1 0 message cueing function enable message cueing disable message cueing c1 iab [ 1 ] = = 1 0 ignore address bit ignore input address register (a0-a15) use the input address register (a0-a15) c2 pu = = 1 0 power up power-up power-down c3 p/ r = = 1 0 playback or record play record c4 run = = 1 0 enable or disable an operation start stop address bits a0-a15 input address register table 4: spi output registers output bits description ovf overflow eom end-of-message p0-p15 output of the row pointer register [1] when iab (ignore address bit) is set to 0, a playback or record operation starts from address (a0-a15). for consecutive playback or record, iab should be changed to a 1 before the end of t hat row (see rac timing). otherwise the ISD4004 will repeat the operation from the same row addre ss. for memory management, the row address clock (rac) signal and iab can be us ed to move around the memory segments. www.datasheet.co.kr datasheet pdf - http://www..net/
ISD4004 series publication release date: oct 31, 2008 - 17 - revision 1.31 message cueing message cueing (mc) allows the user to skip thr ough messages, without knowing the actual physical location of the messages. it will stop when an eom ma rker is reached. then, the internal address counter will point to the next message. also, it will enter into ovf condition when it reaches the end of memory. in this mode, the messages are ski pped 1,600 times faster than the normal playback mode. power-up sequence the ISD4004 will be ready for an operation after pow er-up command is sent and followed by the t pud timing (25 ms for 8 khz sampling rate). refer to the ac timing table for other t pud values with respect to different sampling rates. the following sequences are recommended for optimized record and playback operations. record mode 1. send powerup command. 2. wait t pud (power-up delay). 3. send powerup command. 4. wait 2 x t pud (power-up delay). 5. a). send setrec command with address xx, or b). send rec command (recording from current location). 6. send stop command to stop recording. 7. wait t stop/pause. for 3 & 4), please refer to apps brief 39a: recorded pop elimination in the isd4000 series. for 5.a), the device will start recording at addr ess xx and will generate an interrupt when an overflow (end of memory array) is reached, if no stop co mmand is sent before that. then, it will automatic stop recording operation. playback mode 1. send powerup command 2. wait t pud (power-up delay) 3. a). send setplay command with address xx, or b). send play command (playback from current location). 4. a). send stop command to halt the playback operation, or b). wait for playback operation to stop autom atically, when an eom or ovf is reached. 5. wait t stop/pause. for 3.a), the device will start playback at addre ss xx and it will generate an interrupt when an eom or ovf is reached. it will then stop playback operation. www.datasheet.co.kr datasheet pdf - http://www..net/
ISD4004 series publication release date: oct 31, 2008 - 18 - revision 1.31 7. timing diagrams t ssh t ssmin t sckhi t sss t dis t dih t scklow t pd t pd t df (tristate) lsb ss sclk mosi miso figure 5: timing diagram ss sclk mosi miso a8 a9 a10 c0 c1 c2 c3 c4 ovf eom p0 p1 p2 p3 p4 p5 lsb lsb figure 6: 8-bit command format www.datasheet.co.kr datasheet pdf - http://www..net/
ISD4004 series publication release date: oct 31, 2008 - 19 - revision 1.31 miso mosi lsb a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 ss c0 c3 c4 c1 c2 xx x xx p10p9p8 p11 p12 p13 p14 p15 lsb p7p6p5p4p3p2p1p0 eomovf xx xx sclk byte 1 byte 2 byte 3 figure 7: 16-bit command format ss sclk mosi miso ana in data play/record stop data ana out (rec) t stop/pause t (play) stop/pause figure 8: playback/re cord and stop cycle www.datasheet.co.kr datasheet pdf - http://www..net/
ISD4004 series publication release date: oct 31, 2008 - 20 - revision 1.31 8. absolute maximum ratings table 5: absolute maximum ratings (packaged parts) conditions values junction temperature 150c storage temperature range -65c to +150c voltage applied to any pin (v ss ?0.3v) to (v cc +0.3v) voltage applied to any pin (input current limited to 20ma) (v ss ?1.0v) to (v cc +1.0v) voltage applied to mosi, sclk, and ss pins (input current limited to 20ma) (v ss ?1.0v) to 5.5v lead temperature (soldering ? 10 seconds) 300c v cc ? v ss -0.3v to +7.0v table 6: absolute maximum ratings (die) conditions values junction temperature 150c storage temperature range -65c to +150c voltage applied to any pad (v ss ?0.3v) to (v cc +0.3v) voltage applied to any pad (input current limited to 20 ma) (v ss ?1.0v) to (v cc +1.0v) voltage applied to mosi, sclk, and ss pins (input current limited to 20ma) (v ss ?1.0v) to 5.5v v cc ? v ss -0.3v to +7.0v note: stresses above those listed may cause permanent damage to the device. ex posure to the absolute maximum ratings may affect device reliability and perform ance. functional operation is not implied at these conditions. www.datasheet.co.kr datasheet pdf - http://www..net/
ISD4004 series publication release date: oct 31, 2008 - 21 - revision 1.31 8.1. o perating c onditions table 7: operating conditions (packaged parts) conditions values commercial operating temperature range (case temperature) 0c to +70c industrial operating temperature (cas e temperature) -40c to +85c supply voltage (v cc ) [1] +2.7v to +3.3v ground voltage (v ss ) [2] 0v table 8: operating conditions (die) conditions values commercial operating temperature range 0c to +50c supply voltage (v cc ) [1] +2.7v to +3.3v ground voltage (v ss ) [2] 0v [1] v cc = v cca = v ccd [2] v ss = v ssa = v ssd www.datasheet.co.kr datasheet pdf - http://www..net/
ISD4004 series publication release date: oct 31, 2008 - 22 - revision 1.31 9. electrical characteristics 9.1. p arameters f or p ackaged p arts table 9: dc parameters parameters symbols min [2] typ [1] max [2] units conditions input low voltage v il v cc x 0.2 v input high voltage v ih v cc x 0.8 v output low voltage v ol 0.4 v i ol = 10 a rac, int output low voltage v ol1 0.4 v i ol = 1 ma output high voltage v oh v cc - 0.4 v i oh = -10 a operating current - playback - record i cc 15 25 30 40 ma ma r ext = [3] r ext = [3] standby current i sb 1 10 a [3] [4] input leakage current i il 1 a miso tri-state current i hz 1 10 a output load impedance r ext 5 k ? ana in+ input resistance r ana in+ 2.2 3.0 3.8 k ? ana in- input resistance r ana in- 40 56 71 k ? ana in+ or ana in- to aud out gain a arp 23 db 32 mvpp 1 khz sinewave input [5] notes: [1] typical values @ t a = 25c and v cc = 3.0v. [2] all min/max limits are guaranteed by nuvoton via electronical testing or characterization. not all specifications are 100 percent tested. [3] v cca and v ccd connected together. [4] ss = v cca = v ccd , xclk = mosi = v ssa = v ssa and all other pins floating. [5] measured with automute feature disabled. www.datasheet.co.kr datasheet pdf - http://www..net/
ISD4004 series publication release date: oct 31, 2008 - 23 - revision 1.31 table 10: ac parameters (packaged parts) characteristic symbols min [2] typ [1] max [2] units conditions sampling frequency ISD4004-08m ISD4004-10m ISD4004-12m ISD4004-16m f s 8.0 6.4 5.3 4.0 khz khz khz khz [5] [5] [5] [5] filter pass band ISD4004-08m ISD4004-10m ISD4004-12m ISD4004-16m f cf 3.4 2.7 2.3 1.7 khz khz khz khz 3 db roll-off point [3][7] 3 db roll-off point [3][7] 3 db roll-off point [3][7] 3 db roll-off point [3][7] record duration ISD4004-08m ISD4004-10m ISD4004-12m ISD4004-16m t rec 8 10 12 16 min min min min [6] [6] [6] [6] playback duration ISD4004-08m ISD4004-10m ISD4004-12m ISD4004-16m t play 8 10 12 16 min min min min [6] [6] [6] [6] power-up delay ISD4004-08m ISD4004-10m ISD4004-12m ISD4004-16m t pud 25 31.25 37.5 50 msec msec msec msec stop or pause in record or play ISD4004-08m ISD4004-10m ISD4004-12m ISD4004-16m t stop or t pause 50 62.5 75 100 msec msec msec msec rac clock period ISD4004-08m ISD4004-10m ISD4004-12m ISD4004-16m t rac 200 250 300 400 msec msec msec msec [10] [10] [10] [10] rac clock low time ISD4004-08m ISD4004-10m ISD4004-12m ISD4004-16m t racl 25 31.25 37.5 50 msec msec msec msec rac clock period in message cueing mode ISD4004-08m ISD4004-10m ISD4004-12m ISD4004-16m t racm 125 156.3 187.5 250 sec sec sec sec rac clock low time in message cueing mode ISD4004-08m ISD4004-10m ISD4004-12m ISD4004-16m t racml 15.63 19.53 23.44 31.25 sec sec sec sec total harmonic distortion thd 1 2 % 32 mvpp 1 khz sinewave input [11] ana in input voltage v in 32 mv peak-to-peak [4] [8] [9] www.datasheet.co.kr datasheet pdf - http://www..net/
ISD4004 series publication release date: oct 31, 2008 - 24 - revision 1.31 notes: [1] typical values @ t a = 25c, v cc = 3.0v and timing measurement at 50% of vcc level. [2] all min/max limits are guaranteed by nuvoton via electrical testing or characterization. not all specifications are 100 percent tested. [3] low-frequency cutoff depends upon the value of ex ternal capacitors (see pin descriptions) [4] single-ended input mode. in the differential input mode, v in maximum for ana in+ and ana in- is 16 mvp-p. [5] sampling frequency can vary as much as 2.25 percent over the comme rcial temperature and voltage ranges, and ?6/+4 percent over the industrial tem perature and voltage ranges. fo r greater stability, an external clock can be utilized (see pin descriptions) [6] playback and record duration can vary as much as 2.25 percent over the co mmercial temperature and voltage ranges, and ?6/+4 percent over the industrial temperatur e and voltage ranges. for greater stability, an external clock c an be utilized (see pin descriptions) [7] filter specification applies to t he antialiasing filter and t he smoothing filter. theref ore, from input to output, expect a 6 db drop by nature of passing through both filters. [8] the typical output voltage will be approximately 450 mvp-p with v in at 32 mvp-p. [9] for optimal signal quality, this maximum limit is recommended. [10] when a record command is sent, t rac = t rac + t racl on the first row address. [11] measured with automute feature disabled. www.datasheet.co.kr datasheet pdf - http://www..net/
ISD4004 series publication release date: oct 31, 2008 - 25 - revision 1.31 9.2. p arameters f or d ie table 11: dc parameters parameters [6] symbols min [2] typ [1] max [2] units conditions input low voltage v il v cc x 0.2 v input high voltage v ih v cc x 0.8 v output low voltage v ol 0.4 v i ol = 10 a rac, int output low voltage v ol1 0.4 v i ol = 1 ma output high voltage v oh v cc - 0.4 v i oh = -10 a operating current -playback -record i cc 15 25 30 40 ma ma r ext = [3] r ext = [3] standby current i sb 1 10 a [3] [4] total harmonic distortion thd 1 2 % 32 mvpp 1 khz sinewave input [5] ana in+ or ana in- to aud out gain a arp 23 db 32 mvpp 1 khz sinewave input [5] notes: [1] typical values @ t a = 25c and v cc = 3.0v. sampling frequency can vary as much as 2.25 percent over the commercial temperature and voltage ranges. [2] all min/max limits are guaranteed by nuvoton via electrical testing or characterization. not all specifications are 100 percent tested. [3] v cca and v ccd connected together. [4] = v cca = v ccd , xclk = mosi = v ssa = v ssa and all other pins floating. ss [5] measured with automute feature disabled. [6] the test coverage for die is limited to room temperat ure testing. the test conditions may differ from that of packaged parts. www.datasheet.co.kr datasheet pdf - http://www..net/
ISD4004 series publication release date: oct 31, 2008 - 26 - revision 1.31 9.3. spi ac p arameters table 12: ac parameters [1] parameter symbol min typ max units conditions setup time t sss 500 nsec ss ss hold time t ssh 500 nsec data in setup time t dis 200 nsec data in hold time t dih 200 nsec output delay t pd 500 nsec output delay to highz [2] t df 500 nsec ss high t ssmin 1 sec sclk high time t sckhi 400 nsec sclk low time t scklow 400 nsec clk frequency f 0 1,000 khz notes: [1] typical values @ t a = 25 c, v cc = 3.0v and timing measurement at 50% of vcc level. [2] tri-state test condition. miso v cc 6.32k 10.91k 50pf (includes scope and fixture capacitance) www.datasheet.co.kr datasheet pdf - http://www..net/
ISD4004 series publication release date: oct 31, 2008 - 27 - revision 1.31 10. typical application circuit these application examples are for illustration pur poses only. nuvoton makes no representation or warranty that such application will be suitable for production. make sure all bypass capacitors are as close as possible to the package. 68hc705c8p ISD4004 15-30 pf c9 15-25 pf c8 10 k r7 47 k r6 47 k r5 39 38 1 2 37 35 11 10 9 8 7 6 5 4 19 18 17 16 15 14 13 12 21 22 23 24 25 26 27 28 34 33 32 31 30 29 3 2 28 1 16 17 24 25 26 14 13 11 12 23 18 4 27 13 14 5 6 7 3 2 16 9 8 4 1 12 15 10 11 c11 0.1 f c10 0.1 f c5 1 f c4 1 f c3 0.1 f c2 0.1 f c1 22 f v cc r1 10k r2 1m r3 100 r4 100k pot line out ext speaker c6 1 f c7 .1 f j4 3 2 4 5 1 3 2 1 3 4 5 1 j1 u 3 u 1 u 2 lm4860m ocs1 ocs2 reset irq tcap tcmp pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pd7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pd0/rdi pd1/td0 pd2/miso pd3/mosi pd4/sck pd5/ss miso mosi sclk ss ana in- ana in+ rac int xclk am cap v ccd v ssd v cca v ssa v ssa v ssa aud out -in +in bypass hp-in1 hp-in2 hpsense shutdown gain-out v01 v02 v dd gnd gnd gnd gnd gnd pdip / soic v cc v cc 2 figure 9: application example using spi www.datasheet.co.kr datasheet pdf - http://www..net/
ISD4004 series publication release date: oct 31, 2008 - 28 - revision 1.31 cop 820c ISD4004 r7 23 24 6 5 25 19 20 21 22 3 2 28 1 16 17 24 25 26 14 13 11 12 23 18 4 27 13 14 5 6 7 3 2 16 9 8 4 1 12 15 10 11 c9 0.1 f c8 0.1 f c5 1 f c4 1 f c3 0.1 f c2 0.1 f c1 22 f v cc r1 10k r2 1m r3 100 r4 100k pot line out ext speaker c6 1 f c7 .1 f j4 3 2 4 5 1 3 2 1 3 4 5 1 j1 u 3 u 1 u 2 lm4860m gnd reset v cc cli d3 d2 d1 d0 miso mosi sclk ss ana in- ana in+ rac int xclk am cap v ccd v ssd v cca v ssa v ssa v ssa aud out -in +in bypass hp-in1 hp-in2 hpsense shutdown gain-out v01 v02 v dd gnd gnd gnd gnd gnd pdip / soic c10 4.7 k r6 4.7 k r5 10 11 12 13 3.3 k 82 pf 7 8 9 10 g3 g2 g1 int si sk g7 so l7 l6 l5 l4 l3 l2 l1 l0 11 12 13 14 15 16 17 18 1 4 2 3 26 27 28 v cc 2 v cc v cc figure 10: application example using microwire www.datasheet.co.kr datasheet pdf - http://www..net/
ISD4004 series publication release date: oct 31, 2008 - 29 - revision 1.31 pic16c62a ISD4004 r7 8 1 20 14 16 15 3 2 28 1 16 17 24 25 26 14 13 11 12 23 18 4 27 13 14 5 6 7 3 2 16 9 8 4 1 12 15 10 11 c9 0.1 f c8 0.1 f c5 1 f c4 1 f c3 0.1 f c2 0.1 f c1 22 f v cc r1 10k r2 1m r3 100 r4 100k pot line out ext speaker c6 1 f c7 .1 f j4 3 2 4 5 1 3 2 1 3 4 5 1 j1 u 3 u 1 u 2 lm4860m v ss mclr v dd rc4 rc5 rc3 miso mosi sclk ss ana in- ana in+ rac int xclk am cap v ccd v ssd v cca v ssa v ssa v ssa aud out 19 v ss osc1 3.3 k 9 rc4 rb0 rc0 11 21 7 v cc -in +in bypass hp-in1 hp-in2 hpsense shutdown gain-out v01 v02 v dd gnd gnd gnd gnd gnd pdip / soic c10 4.7 k r6 4.7 k r5 2 v cc v cc figure 11: application example using spi port on microcontroller www.datasheet.co.kr datasheet pdf - http://www..net/
ISD4004 series publication release date: oct 31, 2008 - 30 - revision 1.31 11. packaging and die information 11.1. 28-l ead 300-m il p lastic s mall o utline ic (soic) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 45 67 8 910 11 12 13 14 a d e f b g c h inches millimeters min nom max min nom max a 0.701 0.706 0.711 17.81 17.93 18.06 b 0.097 0.101 0.104 2.46 2.56 2.64 c 0.292 0.296 0.299 7.42 7.52 7.59 d 0.005 0.009 0.0115 0.127 0.22 0.29 e 0.014 0.016 0.019 0.35 0.41 0.48 f 0.050 1.27 g 0.400 0.406 0.410 10.16 10.31 10.41 h 0.024 0.032 0.040 0.61 0.81 1.02 note: lead coplanarity to be within 0.004 inches. www.datasheet.co.kr datasheet pdf - http://www..net/
ISD4004 series publication release date: oct 31, 2008 - 31 - revision 1.31 11.2. 28-l ead 600-m il p lastic d ual i nline p ackage (pdip) inches millimeters min nom max min nom max a 1.445 1.450 1.455 36.70 36.83 36.96 b1 0.150 3.81 b2 0.065 0.070 0.075 1.65 1.78 1.91 c1 0.600 0.625 15.24 15.88 c2 0.530 0.540 0.550 13.46 13.72 13.97 d 0.19 4.83 d1 0.015 0.38 e 0.125 0.135 3.18 3.43 f 0.015 0.018 0.022 0.38 0.46 0.56 g 0.055 0.060 0.065 1.40 1.52 1.62 h 0.100 2.54 j 0.008 0.010 0.012 0.20 0.25 0.30 s 0.070 0.075 0.080 1.78 1.91 2.03 q 0 15 0 15 www.datasheet.co.kr datasheet pdf - http://www..net/
ISD4004 series publication release date: oct 31, 2008 - 32 - revision 1.31 11.3. 28-l ead 8 x 13.4 mm p lastic t hin s mall o utline p ackage (tsop) t ype 1 - iqc a a a 2 1 l l 1 y e h d d b e c min. dimension in inches nom. max. min. nom. max. symbol 1.20 0.05 0.15 1.05 1.00 0.95 0.17 0.10 11.70 7.90 13.20 0.50 0.00 0 0.20 0.27 0.15 0.21 11.80 11.90 8.00 8.10 13.40 13.60 0.55 0.60 0.70 0.80 0.10 35 0.047 0.006 0.041 0.040 0.035 0.007 0.008 0.011 0.004 0.006 0.008 0.461 0.465 0.469 0.311 0.315 0.319 0.520 0.528 0.536 0.022 0.020 0.024 0.028 0.031 0.000 0.004 035 0.002 a a b c d e e l l y 1 1 2 a h d dimension in mm www.datasheet.co.kr datasheet pdf - http://www..net/
ISD4004 series publication release date: oct 31, 2008 - 33 - revision 1.31 11.4. 28-l ead 8 x 13.4 mm p lastic t hin s mall o utline p ackage (tsop) t ype 1 utline p ackage (tsop) t ype 1 5 6 7 8 9 10 11 12 13 14 2 3 4 15 16 17 18 19 20 21 22 23 24 25 26 27 28 a b inches millimeters min nom max min nom max a 0.520 0.528 0.535 13.20 13.40 13.60 b 0.461 0.465 0.469 11.70 11.80 11.90 c 0.311 0.315 0.319 7.90 8.00 8.10 d 0.002 0.006 0.05 0.15 e 0.007 0.009 0.011 0.17 0.22 0.27 f 0.0217 0.55 g 0.037 0.039 0.041 0.95 1.00 1.05 h 0 3 6 0 3 6 i 0.020 0.022 0.028 0.50 0.55 0.70 j 0.004 0.008 0.10 0.21 note: lead coplanarity to be within 0.004 inches. g f c d e h j a b g 4 8 10 1 2 3 5 6 7 9 11 12 13 14 18 20 24 17 16 15 19 21 22 23 25 26 27 28 f c e j h i www.datasheet.co.kr datasheet pdf - http://www..net/
ISD4004 series publication release date: oct 31, 2008 - 34 - revision 1.31 11.5. d ie i nformation ISD4004 series o die dimensions (with scribe line) [1] x: 166.6 1 mils y: 385.0 1 mils miso mosi ss v ccd sclk int rac v ssa v ssd v ssd v ccd xclk ISD4004 v cca [3] ana in+ am cap aud out v ssa [3] v ssa ana in- v ssa [3] v cca [3] o die thickness [2] 11.5 0.5 mils o pad opening single pad: 90 x 90 microns double pad: 180 x 90 microns notes: [1] the backside of die is internally connected to v ss . it must not be connected to any other potential or damage may occur. [2] die thickness is subject to change, please contact nuvoton as this thickness may change in the future. [3] double bond is recommended if treated as one pad. www.datasheet.co.kr datasheet pdf - http://www..net/
ISD4004 series publication release date: oct 31, 2008 - 35 - revision 1.31 ISD4004 s eries p ad c oordinations (with respect to die center) pad pad description x axis (m) y axis (m) v ssa analog ground 1885.2 4623.7 rac row address clock 1483.8 4623.7 int interrupt 794.8 4623.7 xclk external clock input 564.8 4623.7 v ccd digital power supply 387.9 4623.7 v ccd digital power supply 169.5 4623.7 sclk slave clock -14.7 4623.7 ss slave select -198.1 4623.7 mosi master out slave in -1063.7 4623.7 miso master in slave out -1325.6 4623.7 v ssd digital ground -1665.3 4623.7 v ssd digital ground -1836.9 4623.7 v ssa [1] analog ground -1943.1 -4622.4 v ssa [1] analog ground -1853.1 -4622.4 v ssa analog ground -1599.9 -4622.4 aud out audio output 281.9 -4622.4 am cap automute 577.3 -4622.4 ana in- inverting analog input 1449.3 -4622.4 ana in+ noninverting analog input 1603.5 -4622.4 v cca [1] analog power supply 1853.7 -4622.4 v cca [1] analog power supply 1943.7 -4622.4 note: [1] double bond recommended if treated as one pad. www.datasheet.co.kr datasheet pdf - http://www..net/
ISD4004 series publication release date: oct 31, 2008 - 36 - revision 1.31 12. ordering information ISD4004- product family : product series : isd4000 family 04 = fourth series (8-16 min) duration : 08m = 8 minutes 10m = 10 minutes 12m = 12 minutes 16m = 16 minutes special temperature field : blank = commercial package (0c to + 70c) or commercial die (0c to + 50c) i = industrial (-40c to + 85c) packaged units / die : x = die p = 28-lead 600-mil plastic dual inline package (pdip) s = 28-lead 300-mil plastic small outline package (soic) when ordering the devices, please refer to the fo llowing valid ordering numbers and contact the local nuvoton sales representatives for availability. when ordering the devices, please refer to the fo llowing valid ordering numbers and contact the local nuvoton sales representatives for availability. type duration 8 minutes 10 minutes 12 minutes 16 minutes package part # order # part # order # part # order # part # order # die ISD4004-08mx i4408x ISD4004-10mx i4410x ISD4004-12mx i4412x ISD4004-16mx i4416x lead-free pdip ISD4004-08mpy i4408py ISD4004-10mpy i4410py ISD4004-12mp i4412py ISD4004-16mpy i4416py soic ISD4004-08msy i4408sy ISD4004-10msy i4410sy ISD4004-12ms i4412sy ISD4004-16msy i4416sy ISD4004-08msyi i4408syi ISD4004-10msyi i4410syi ISD4004- 12msi i4412syi ISD4004- 16msyi i4416syi tsop ISD4004-08mey i4408ey ISD4004-10mey i4410ey ISD4004-12me i4412ey ISD4004-16mey i4416ey ISD4004-08meyi i4408eyi ISD4004-10meyi i4410eyi ISD4004- 12mei i4412eyi ISD4004- 16meyi i4416eyi for the latest product information, access nuvoton worldwide website at http://www.nuvoton-usa.com e = 28-lead 8x13.4mm plastic thin small outline packa g e ( tsop ) t yp e 1 lead-free type: y = lead-free www.datasheet.co.kr datasheet pdf - http://www..net/
ISD4004 series publication release date: oct 31, 2008 - 37 - revision 1.31 13. version history version date description 0 june 2000 initial version 1.0 feb. 2004 reformat the document. add note for typical filter pass band. add memory architecture description. revise rac timing parameter for mc. revise automute: playback only. revise spi, opcodes sections, record & playback steps. rename t raclo to t racl . revise a arp parameter. revise dc & ac parameters tables for die. revise die: (x,y) coordinates. 1.1 apr. 2005 add lead-free parts. revise the ordering information. revise disclaim section. 1.2 oct. 2005 revise packaging information. 1.3 jul. 2007 remove the leaded package option remove the extended temperature option update the external clock description revise ordering information section 1.31 oct 31, 2008 change to nuvoton logo revise miso description www.datasheet.co.kr datasheet pdf - http://www..net/
ISD4004 series publication release date: oct 31, 2008 - 38 - revision 1.31 headquarters nuvoton technology corporation america nuvoton technology (shanghai) ltd. no. 4, creation rd. iii 2727 north first street, san jose, 27f, 299 yan an w. rd. shanghai, science-based industrial park, ca 95134, u.s.a. 200336 china hsinchu, taiwan tel: 1-408-9436666 tel: 86-21-62365999 tel: 886-3-5770066 fax: 1-408-5441797 fax: 86-21-62356998 fax: 886-3-5665577 http://www.nuvoton-usa.com/ http://www.nuvoton.com.tw/ taipei office nuvoton technology corporation japan nuvoton technology (h.k.) ltd. 9f, no. 480, pueiguang rd. 7f daini-ueno bldg. 3-7-18 unit 9-15, 22f, millennium city, neihu district shinyokohama kohokuku, no. 378 kwun tong rd., taipei, 114 taiwan yokohama, 222-0033 kowloon, hong kong tel: 886-2-81777168 tel: 81-45-4781881 tel: 852-27513100 fax: 886-2-87153579 fax: 81-45-4781800 fax: 852-27552064 please note that all data and specifications are subject to change without notice. all the trademarks of products and companies mentioned in this datasheet belong to their respective owners. nuvoton products are not designed, int ended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or fo r other applications intended to support or sustain life. furthermore, nuvoton produc ts are not intended for applications wher ein failure of nuvoton products could result or lead to a situation wherein personal injury, deat h or severe property or environmental damage could occur. nuvoton customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify nuvoton for any damages resulti ng from such improper use or sales. the contents of this document are provided only as a guide for the applications of nuvoton products. nuvoton makes no representation or warranties with respect to the accuracy or completeness of the c ontents of this publication and reserves the right to discontinue or make changes to specif ications and product descriptions at any time without notice. no license, whether express or implied, to any intellectual property or other right of nuvoton or others is granted by this publication. except as set forth in nuvoton's standard terms and conditions of sale, nuvoton assumes no liability whatsoever and disclaims any express or implied warrant y of merchantability, fitness for a particular purpose or infringement of any intellectual property. the contents of this document are pr ovided ?as is?, and nuvoton assumes no liability whatsoever and disclaims any express or implied warranty of merchant ability, fitness for a particular purpose or infringement of any intellectual property. in no event, shall nuvoton be liable for any damages whatsoever (including, wit hout limitation, damages for loss of profits, business interruption, loss of information) arising out of the use of or inability to use the contents of this documents, even if nuvoton has been advis ed of the possibility of such damages. application examples and alternative uses of any integrated circuit contained in this publication are for illustration only and nuvoton makes no representation or warranty that such applications sha ll be suitable for the use specified. the 100-year retention and 100k record cycle projections are based upon accelerated reliability tests, as published in the nuvoton reliability report, and are neither warranted nor guaranteed by nuvo ton. this product incorporates superflash ? . information contained in this isd ? chipcorder ? datasheet supersedes all data fo r the isd chipcorder products published by isd ? prior to august, 1998. this datasheet and any future addendum to this datasheet is(are) the complete and controlling isd ? chipcorder ? product specifications. in the event any inconsistencies exist between the information in this and other product documentation, or in the event that other product documentat ion contains information in addition to the information in this, the information contained herein supersedes and governs su ch other information in its entirety. this datasheet is subject to change without notice. copyright ? 2005, nuvoton technology corporation. all rights reserved. chipcorder ? and isd ? are trademarks of nuvoton technology corporation. superflash ? is the trademark of silicon storage technology, inc. all other trademarks are properties of their respective owners. www.datasheet.co.kr datasheet pdf - http://www..net/

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